Digital cell for large scale integration

ABSTRACT

There is disclosed an article and method of fabrication thereof comprising an integrated semiconductor circuit in the form of a digital cell of standard configuration suitable for universal use in large scale integrated circuit arrays which may be mass produced up to the final interconnecting metallization step and thereafter stored for use in filling custom orders in accordance with a large variety of interconnection patterns to convert the array of standard digital cells to one of many possible functional systems. Each cell comprises a logic stage or gate circuit of universal applicability which may be interconnected with other similar cells in a large number of different ways to form completed circuits. The multiplicity of possible circuits are in general built by repetitive utilization of &#39;&#39;&#39;&#39;nor&#39;&#39;&#39;&#39; gates, &#39;&#39;&#39;&#39;nand&#39;&#39;&#39;&#39; gates, &#39;&#39;&#39;&#39;transfer&#39;&#39;&#39;&#39; gates and load devices.

Grannis et al.

[ 1 Nov. 13, 1973 DIGITAL CELL FOR LARGE SCALE INTEGRATION Inventors: Norman J. Grannis, Palos Verdes;

Ted Winkler, Inglewood, both of Calif.

Assignee: TRW lnc., Redondo Beach, Calif.

Filed: July 19, 1971' Appl. No.: 164,080

Related US. Application Data Continuation of Ser. No. 669,091, Sept. 20, 1967,

Field of Search 317/235 G; 307/205, 307/21 215 References Cited UNITED STATES PATENTS FOREIGN PATENTS OR APPLICATIONS 1,045,769 10/1966 Great Britain 317/235 Primary Examiner-Jerry D. Craig Attorney-Daniel T. Anderson, Donald C. Keaveney and Gerald Singer [57] ABSTRACT There is disclosed an article and method of fabrication thereof comprising an integrated semiconductor circuit in the form of a digital cell of standard configuration suitable for universal use in large scale integrated circuit arrays which may be mass produced up to the final interconnecting metallization step and thereafter stored for use in filling custom orders in accordance with a large variety of interconnection patterns to convert the array of standard digital cells to one of many possible functional systems. Each cell comprises a logic stage or gate circuit of universal applicability. which may be interconnected with other similar cells in a large number of different ways to form completed circuits. The multiplicity of possible circuits are in general built by repetitive utilization of nor gates, nand gates, transfer gates and load devices.

5 Claims, 40 Drawing Figures 4Q I62 I39 Q Q5 G2 I CD:

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DIGITAL CELL FOR LARGE SCALE INTEGRATION This application is a continuation of copending application Ser. No. 669,091, filed Sept. 20, I967, now abandoned.

BACKGROUND OF THE INVENTION The techniques used in what is commonly referred to as microelectronics have achieved not merely a large reduction in weight and size of electronic components and circuits, but have also achieved and are continuing to increasingly achieve reductions in cost and improvements in reliability which make-practical an entirely new order of allowable system complexity. One important approach to microelectronics is provided by semiconductor integrated circuitry, the technology of which sprang naturally from transistor and diode technology.

The term semiconductor integrated circuitry has been applied-to a wide variety of levels of sophistication. Two extremes, for example, are the chip approach wherein individual components such as transistors, resistors, and diodes are produced on separate pieces of material. These separate components are then mounted and interconnected in a single package to produce a circuit function by what is really a microassembly technique. The other extreme produces the entire electronic function in and upon a single piece of semiconductor material having many components or regions in the monolithic wafer that are isolated or interconnected electrically as the circuit requires. Normally, in this monolithic approach all the intraconnections within the functional block will be made by batch processing on large numbers of circuits. The only individual assembly operations are associated with mounting the final circuit function wafer in a package so that it can be connected conveniently to the outside world.

The chip or microcomponent approach, of course, has the advantage of affording high volume mass production of the individual components which can later be connected in a large number of different circuits to meet a plurality of market needs or applications. On the other hand, the monolithic functional wafer approach has distinct advantages of reliability, size, weight, and cost per total circuit function assuming a sufficient level of demand for the particular circuit of greater complexity and hence more specific and limited applicability.

Examples of producing semiconductor devices in a monolithic wafer are shown by the U. S. Pat. to Axelrod, No. 3,406,298 and Mayhew, No. 3,365,707. Axel-' rod notes that a large number of active devices may be placed onto a single wafer along with functional interconnections to form operative circuit arrangements, including a NOR function circuit having a resistive load created by interconnecting field effect transistors. Mayhew disclosed that two unconnected sets of paired transistors having an unconditional connection point associated with each pair may be repeatedly formed into an array upon a single wafer. External metalization interconnections between the sets and other like sets may then be made to form logical operations.

It is an object of this invention to provide an article and method of fabrication thereof which retains the above-noted advantages of the monolithic wafer approach to semiconductor integrated circuits while yet achieving most of the flexibility and high volume economy inherent in the microcomponent or chip techmque.

It is a further object of this invention to provide a digital cell comprising a universal logic circuit having a plurality of terminals available from a gate circuit arrangement formed in a monolithic semiconductor wafter.

It is a still further object of this invention to provide a digital cell comprising a logic stage of universal applicability from which many more complex circuits may be fabricated by simple interconnection of appropriate pre-existing available terminals in order to facilitate large scale integration at reasonable cost of circuits of greater complexity than has heretofore been feasible.

SUMMARY OF THE INVENTION These and other objects and advantages are achieved, as will be more apparent from the detailed discussion below, by providing an integrated circuit semiconductor wafer comprising a plurality of Metal Oxide Silicon Field Effect Transistors formed in a digital cell circuit which itself is repeated as many times on a single substrate as is practical; and then, in a later separate process, interconnecting the available terminals from each cell in such a manner as to form the parts of a digital machine such as an electronic computer, data processor, telemetry equipment or the like. The digital cellis designed to serve as a building block of universal applicability in a very large number of circuits. In complexity it is midway between the traditional concept of a component and the concept of a full integrated circuit. It thus shares many of the advantages of both and makes large scale integration economically practical.

Each digital cell, in a preferred embodiment comprises five P-channel enhancement mode Metal-Oxide- Silicon Field Effect Transistors connected to form a logic circuit. Provision for interconnection to other identical cells is provided by eight bonding pads. The cell may be used alone or in combination with other identical cells to form NOR gates, OR gates, R-S flipflops, .I-K flip-flops, binary flip-flops, exclusive OR gates, shift registers, active memories and other digital logic elements. A four cell chip measures approximately 62 X 65 mils. More than 500 cells can easily be formed in a single wafer. In a preferred embodiment the average power dissipation per cell wastypically 3 milliwatts and the average propagation delay was less than 200 nanoseconds.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) 1(k), 1(m) and 1(n) a series ofcut-away isometric views illustrating the process by which a typical single field effect transistor of the type used herein is manufactured. Exemplary masks used in the process are shown at views 1(b), 1(e), 1(h), and 1(k). The remaining views illustrate the effect on the initial block of material shown in view (a) of the steps performed using the masks.

FIG. 2 is a schematic view defining a diagram used throughout the drawings to indicated an MOS field effect transistor of the type shown in FIG. 1(n) as manufactured by the process illustrated in FIG. 1.

FIG. 3 is a schematic circuit diagram, showing the circuit configuration of one embodiment of a digital cell in accordance with the present invention.

FIG. 4 is a circuit diagram showing the circuit configuration of a second embodiment of a digital cell in accordance with he present invention.

FIG. 5 is a plan view of a mask similar to that used in the exemplary view of FIG. l(b), but showing the actual mask layout of the source and drain forming step in producing a cell in accordance with the circuit diagram of FIG. 3.

FIG. 6 is a view similar to FIG. 5 but showing the second or gate mask used in the manufacture of the digital cell in accordance with the circuit diagram of FIG. 3.

FIG. 7 is a view similar to FIGS. 5 and 6 showing the third or contact mask used in manufacturing a digital cell in accordance with the circuit diagram of FIG. 3.

FIG. 8 is a view similar to FIG. 7 but showing the fourth or interconnection mask used in forming a digital cell in accordance with the circuit diagram of FIG. 3.

FIG. 9 is a circuit diagram of a four cell chip of the type manufactured by the use of the masks shown in FIGS. 5, 6, 7, and 8, wherein four circuits of the type shown in FIG. 3 are interconnected on a single chip.

FIGS. 10 through 18 are each circuit diagrams illustrating various exemplary circuit configurations which may be formed from the digital cell previously described by appropriate interconnections. Associated with each figure is a graph showing voltage plotted as a function of time for various inputs and outputs to illustrate the function of the circuit.

FIG. 10(a) shows the connection for a three-input NOR gate.

FIG. [1(a) shows the circuit connection using two digital cells to form a three-input OR gate.

FIG. 12(a) shows the circuit connections for using two digital cells to form an R-S flip-flop circuit.

FIG. l3(a) shows the circuit connections for using three digital cells to form an exclusive OR gate.

FIG. 14(a) shows the circuit connections for using two digital cells in a dynamic shift register.

FIG. 15(a) shows the circuit connections for using two digital cells in a dynamic shift register with a delayed latch pulse.

FIG. 16(a) shows the circuit connection for using four digital cells to form a two flip-flop binary.

FIGS. 10(b)-l6(b) show waveforms for the cells of FIGS. l0(a)-l6(a), respectively.

FIG. 17(a) shows the circuit configuration for using six digital cells to form a three flip-flop binary.

FIG. 17(b) and 17(c) are graphs of alternate possible input and output voltage to the circuit of FIG. 17.

FIG. 18(a) shows the circuit configuration for using 19 digital cells including 58 transistors to form a four bit ring counter.

FIG. 18(b) shows the waveforms for the cells of FIG. 18(a).

DESCRIPTION OF THE PREFERRED EMBODIMENTS Although the digital cell circuit referred to above could be implemented with many different kinds of active elements such as bipolar junction transistors in either integrated or discrete component form, it is presently preferred to fabricate the digital cell circuit from Metal Oxide Silicon Field Effect Transistors which have been formed in a monolithic silicon wafer, since this integrated circuit version of the MOSFET affords the maximum manufacturing advantages and economics and the maximum flexiblity of application for the circuit described herein. Since this is, in fact, the preferred form, a brief description will first be given of the structure and principles of operation of a single Metal Oxide Silicon Field Effect Transistor (hereinafter referred to as a MOSFET). Thereafter, a brief description of the method of manufacturing such a single device will be given in order to simplify this aspect of the description. Subsequent to this, the actual physical layout of the complete integrated circuit digital cell which forms the subject matter of the invention will be described. Such an actual cell is, of course, manufactured by the same process as that used for a single cell, the only difference being in the complexity of the structures, which aspect will be isolated for separate discussion. Finally, there will be described and illustrated a number of exemplary applications which can be derived from the digital cell by making appropriate interconnections between various numbers of cells.

In FIG. l(m) there is shown a cut away perspective view of a single MOSFET and in FIG. l(n) there is shown an enlarged cross-sectional view of the device of FIG. l(m). In these two views there is shown a semiconductor wafer 20 which comprises a substrate of N- type silicon. Formed in this N-type substrate is a source region 21 and a drain region 22. Both the source and drain are formed of P+ type silicon and are spearated by an area 23 of N-type silicon which functions as a conduction channel under appropriate operating conditions. The P+ regions forming the source and drain are formed in the silicon wafer by diffusion steps to be described in greater detail below. Above the surface of the wafer is a layer 24 of silicon dioxide. Layer 24 has etched through it holes through which contact is made to the source and drain regions by aluminum interconnect or contact material. Thus, contact area 25 extends through the silicon dioxide to form the source elec trode whereas the contact 26 extends through the silicon dioxide to form the drain electrode. The gate electrode 27 is separated from electrodes 25 and 26 electrically and is positioned above the channel area 23. The gate electrode 27 normally has input signal voltage applied to it and forms with the area 23, the two plates of the capacitor of which the thin silicon dioxide layer between electrode 27 and channel 23 forms the dielectric.

The device shown in FIGS. l(m) and l(n) is commonly illustrated in circuit diagrams in the art in the manner shown in FIG. 2. This schematic circuit representation will be used throughout this specification. It will be noted in FIG. 2 that the gate electrode 27 and the source and drain electrodes 25 and 26 represent parts having corresponding reference characters in FIG. l(m). Not only does this device afford many advantages from a manufacturing point of view but also it is a semiconductor transistor device which is capable of combining the high input impedance ofa typical vacuum tube with many of the advantages offered by junction transistors, such as the ability to be DC coupled without level shifting.

The name MOS is derived from the sandwich-like structure of Metal (usually aluminum), Oxide (SiO and Silicon shown in FIGS. l(m) and l(n). The metal forms the central electrode 27 which we have called the gate and is isolated from the body of the device by a thin but very non-conductive layer of silicon oxide 24. This oxide layer accounts for the extremely high input resistance of the device which it typically as great as ohms. The metal gate electrode 27 is separated from the body of the device by a layer of silicon dioxide of about 1,000 Angstrom thickness. The gate and body thus form a parallel plate capacitor, the silicon dioxide forming a dielectric layer between the two plates. The semiconductor region 23 directly beneath the gate is called the channel.

When no charge is on the gate, the channel is N-type silicon, since it is an integral part of the N-type body or substrate. In this condition, if a potential is applied between source and drain, no current will flow, because, regardless of the polarity of the applied potential, one of the P-N junctions formed by the source, body and drain will be reverse biased.

If the gate is charged negative with respect to body and source, an equal amount of positive charge must accumulate in the channel region. This positive charge (in the form of holes) comes mainly from the source. The presence of the induced holes in the channel region begins to shift the channel from the N-type towards the P-type.

The gate voltage (V at which just enough induced charge is present to make the channel change from N to P is called the threshold voltage. At this point, the P-N junctions between source, channel and drain disappear at the surface and ohmic conduction between source and drain can occur in either direction. The conductivity will be very slight, however, since only a very thin surface layer of the channel will be inverted. As the gate is made more and more negative, the inverted layer will go deeper and deeper, increasing conductivity from source to drain.

The simplest possible model for this behavior is de rived by considering the channel to be a uniform conducting slab of length L width w and thickness h, where h depends on the gate voltage, V The source and drain make ohmic contact to the channel. The resistance from the source to the drain is then given by:

R p L/w h where p is the resistivity of the slab and is assumed constant. If one further assumes that the thickness of the slab is simply proportional to the charge induced in the channel, minus the charge necessary to-make the channel change from N to P (i.e., the charge induced by the threshold voltage), EQuation 1 becomes:

where K is a proportionality constant. For a given geometry, p, L, w, and K are all constants so that equation 2 can be written:

where K is a constant.

Thus, a graphic plot of R versus V at a constant drain voltage shows a l/X characteristic since R varies inversely as V In this sense, then, the device can be thought of as a voltage controlled variable resistor, the value of which is controlled by the gate voltage. The resistance between the source and the drain remains very high (often 10 ohms) as the gate is made more and more negative until the threshold voltage of the device is reached. At this point, the resistance decreases rapidly. The resistance continues to decrease with more negative gate voltage but the rate of change diminishes and the resistance approaches a limiting value which is determined by the geometry of the device. The threshold voltage is an important characteristic. It is this property which gives digital circuits employing MOS transistors their extremely high noise immunity. Noise signals which would saturate regular bipolar transistors are completely rejected by the MOST if they are below the threshold which is approximately 4 volts.

In summary then, the MOST has higher input resistance than the best vacuum tubes but can be DC coupled'without the need of level shifting. It has much higher noise immunity than bipolar transistors, but still maintains the advantages of low power, small physical size, rugged construction, and ability to operate without filaments. These characteristics render the device ideally suited for the fabrication of large scale integrated digital circuitry. As has been noted originally above, such large scale integration is best achieved by fabrication of the digital cell of the present invention comprising an interconnected group of MOS transistors.

For a more complete discussion of the characteristics and a more rigorous theoretical analysis of the performance of Metal Oxide Silicon Field Effect Transistors, reference is made to an article by C. T. Sah which was published in the Transactions of Electron Devices by the Institute of Electrical and Electronics Engineer, under the title, Characteristics of the Metal-Oxide-Semiconductor Transistor," in July 1964 and which appeared on pages 324 through 345 of the Transactions on Electron Devices.

For purposes of illustration of a suitable manufacturing process, there will first be described the series of manufacturing steps by which a device of the type described above and shown in FIGS. 1(m) and (n) and indicated by the schematics of FIG. 2 can be manufactured. For a more complete discussion of general conventional manufacturing techniques which will be assumed herein, reference is made to a book entitled, Microelectronics, edited by Edward Keonjian and published by the McGraw Hill Book Company of New York in 1963. Reference is particularly made to pages 289 through 301 for a discussion of known photolithographic techniques of surface geometry control, techniques of metallization for interconnection and packaging techniques.

Turning now to FIG. 1(a) through 1(n), it will be seen from FIG. 1(a) that a layer 24 of silicon oxide (SiO is first thermally grown on an N-type silicon wafer 20. Next, there is applied to the upper surface of layer 24 a photoresist solution which is not illustrated as such in the drawing. Suitable solutions and techniques for this step are described, for example, on pages 289 and 290 of the Keonjian book. As pointed out therein, these resists are photosensitive materials which act as a mask against chemical etchants. The resists are usually low molecular weight organic compounds which polymerize when subjected to ultraviolet radiation. This radiation is applied through a mask which may, for example, be of the type shown in FIG. 1(b) as the mask 31 defining the source and drain areas for the exemplary device. The mask is, of course, registered with the entire surface to be exposed and has opaque portions in the areas where it is later desired to etch through the silicon oxide layer 24. Since the ultraviolet light does not penetrate these opaque areas, the resist material under them is not polymerized and is therefore readily removed from the surface after the exposure to ultraviolet. The portions of the surface which lie under the transparent areas of the mask 31 receive the ultraviolet light which polymerizes the resist material and causes it to adhere to the surface strongly enough to resist ordinary washing techniques. This resist material forms a mask over the silicon oxide layer which mask is not penetrated by etchant material later used to etch away the exposed portions of the silicon oxide.

After the unwanted photoresist lying under the opaque portions of the mask have been removed, an etching solution is applied to etch the silicon oxide layer 24 down to the silicon over the areas in which it is desired to form the source and drain of the MOST. The usual etchant is buffered hydroflueric acid.

The source and drain areas 21 and 22 are then formed in the wafer 20 by thermal diffusion of a suitable impurity element in the areas etched away after exposure through the mask 31. The result of the above series of steps is shown in FIG. 1(0). The polymerized resist is next stripped off by any suitable stripping solution. The etching, silicon oxide masking, and thermal diffusion and stripping steps are all conventional and well known in the art. Afterthe source and drain areas 21 and 22 are formed, the etched away areas of the silicon oxide layer are re-oxidized to produce the structure shown in FIG. 1(d) wherein the etched away areas of layer 24 have been regrown as at 24(b) and 24(0) to again afford a continuous silicon oxide mask over which photoresist solution is again applied.

The regrown solid surface which has again been coated with photoresist is then exposed to ultraviolet light through the gate mask 32 shown in FIG. 1(e). Again, the unwanted photoresist is washed away and the silicon under the gate area is etched down to the silicon layer 20. The device at this stage of processing is shown in FIG. 1(1). The thin silicon oxide layer 24(a) is then regrown over the gate area and above the channel area 23 thereby producing a structure as shown in FIG. 1(g).

Again, the entire stop surface which is coated with silicon oxide is stripped and has a new photoresist layer applied thereto. This photoresist is next exposed through the contact mask shown at 33 in FIG. 1(h). As in earlier steps the unwanted photoresist is removed by washing and the exposed silicon oxide is etched down to the silicon layer at the contact areas defined by the opaque portions 33(a) and 33(b) of mask 33. It will, of course, be understood that conventional means not shown herein are used to properly index or register the positions of masks 31, 32, and 33 so that the multiple exposures have the effect of forming a single related pattern as is common in photolithographic techniques. After the contact areas have been etched away, the device will appear as shown in FIG. 1(i). A layer of aluminum is next deposited over the entire wafer. This aluminum layer is shown in FIG. as the layer 28.

Next, there is applied to the aluminum surface 28 a suitable photoresist layer to prepare for the final photoetching step. This layer is then exposed through the interconnection mask 34 shown in FIG. 1(k). Again, the unwanted photoresist is removed by washing and the metal is etched down to the silicon oxide layer 24 in order to form the interconnect pattern and thereby produce the device as shown in FIG. 1(m). It will be noted that the result of etching away the excess aluminum results in forming from the aluminum sheet 28 three separate electrode contacts, namely, the source contact 25 which extends down through the silicon oxide layer to make contact with the P+ source area 21, the gate electrode 27 which forms with the channel area 23 the two plates of a parallel plate capacitor for which the silicon oxide layer 24(a) forms the dielectric, and the drain electrode 26 which extends down through the silicon oxide layer 24 to make contact with the P+ drain area 22.

After producing the device of FIG. 1(m) by etching, the unwanted photoresist is, as usual, removed by a suitable stripping solvent. After removal of the excess photoresist, the wafer is sintered to provide a low silicon to metal contact resistance. The device is then probe tested to assure operative electrical characteristics as desired. Of course, where in production of the device to be described below a large number of such MOSFETs are produced on a single wafer each of them will be probe tested. The wafer is then diced into chips of a suitable size as desired in accordance with the characteristics below.

As noted above, a device of the type shown in FIGS. 1(m) and 1(n) will be schematically represented hereinafter as shown in FIG. 2. It will, of course, be understood that by wire bonding between terminal pads or by applying over devices of the type shown in FIG. 1(m), a suitable additional insulating layer above which further metalization and interconnect layers may be applied, a number of the individual devices may be interconnected in various desired circuit configurations. Such configurations can also and preferably be formed when a large number of MOSFETs are produced in a single wafer, by using a more elaborate mask in the initial interconnection step illustrated by way of example, by the use of mask 34 and FIG. 1(k). The more nearly completely the finally desired interconnection pattern can be formed in the first contact and interconnection forming step, the more useful the device will be in the sense of having a wider range and greater flexibility of application to various total circuit configurations. Once the final interconnections are made, the device is, of course, packaged and tested in any suitable conventional manner.

In FIGS. 3 and 4 there are shown circuit diagrams of two embodiments of the digital cell of the present invention which are formed by an initial interconnection step of the type described in the process illustrated by FIG. 1. The actual masks used to form this circuit configuration are illustrated in FIGS. 5 and 6, 7 and 8. It will, of course, be understood that the mask of FIG. 5 is used in the same manner as the source and drain mask 31 of FIG. 1(b); that the mask shown in FIG. 6 is used in the same manner as the gate mask 32 shown in FIG. 1(e); that the mask shown in FIG. 7 is used in the same manner as the contact mask 33 shown in FIG. 1(h); and that the mask shown in FIG. 8 is used in the same manner as the interconnection mask 34 shown in FIG. 1(k). These masks and their use will be considered in greater detail below, but consideration should now first be given to the circuit diagrams of FIGS. 3 and 4.

Turning now to FIGS. 3 and 4, there are shown two possible embodiments of the circuit forming the digital 

1. An integrated circuit microelectronic device having a plurality of Metal Oxide Silicon Field Effect Transistors formed in a common substrate of one conductivity type and grouped into standard cells, each cell comprising: a common diffusion region of another conductivity type formed in the substrate; first, second, third, fourth, and fifth diffusion regions of said another conductivity type formed in and arranged peripherally around said common diffusion region, each equally spaced therefrom, thereby defining a channel region therebetween each of equal length, said first and second region being integrally continuous; a layer of dielectric material disposed over the substrate including that region above each of said channel regions; first, second, third, fourth and fifth gate electrodes deposited on said dielectric layer and each having a first portion disposed above the channel region of a respective one of said diffusion regions, and a second portion constituting a terminal bonding pad whereby, respectively, first, second, third, fourth and fifth, metal oxide silicon field effect transistors are provided; output terminal means deposited on said dielectric and having one portion extending through said dielectric into contact with said common diffusion region and having another portion forming a terminal bonding pad; first and second input signal terminal means each deposited on said dielectric layer and each having a portion extending through said dielectric layer into contact with said third and said fourth diffusion regions, respectively; ground terminal means deposited on said dielectric and having a first portion extending through the dielectric into contact with said first and second continuous diffusion regions, a second portion coupled to a corresponding first and second continuous diffusion regions of at least one other cell, and a third portion forming a bonding pad; and power buss means deposited on said dielectric and having a first portion extending through said dielectric into contact with said fifth diffusion region, a second portion coupled to a corresponding fifth diffusion region of at least said one other cell, and a third portion forming a bonding pad whereby a plurality of standard cells having basic logic circuitry therein are provided, each cell having at least five transistors which share a common diffusion region, and with predetermined inter-cell connections form a preselected one of a plurality of functional circuits.
 2. The device of claim 1 wherein the fifth transistor of each said cell further comprises: one segment of said fifth diffusion region spaced from another portion, the region therebetween defining a channel region; and a sixth gate electrode deposited on said dielectric layer and operatively associated with said segments of said fifth diffusion region, and further, said segments, said fifth and sixth gate electrodes and said common diffusion region connected to function as a single high resistance transistor.
 3. The device of claim 2 wherein: said first, second, third, fourth and fifth diffusion region each have widths selected such that resistance ratio of the second transistor, with respect to the resistance of the first transistor, is one, of the third transistor is less than one, of the fourth transistor is greater than one, and of the fifth transistor is at least ten.
 4. The device of claim 3 wherein: said resistance ratio of the third transistor is one-half, the fourth transistor is four, and the fifth transistor is sixteen.
 5. The device of claim 3 further comprising: a sixth diffusion region formed in the substrate proximate said third diffusion region; a seventh diffusion region formed in the substrate proximate said sixth diffusion region and defining a seventh channel region therebetween; a seventh gate electrode deposited on said dielectric layer above said seventh channel region and having a portion forming a terminal bonding pad; said second input signal terminal means having another portion extending through said dielectric and into contact with said sixth diffusion region; and third input signal terminal means deposited on said dielectric and having one portion extending through said dielectric layer and into contact with said seventh diffusion region, and having another portion forming a terminal bonding pad. 